In view of the above, it is an object of the present invention to provide a VCO circuit of which fluctuation of the frequency Fo of an output signal is small even when a power supply voltage fluctuates. In addition, it is an object of the present invention to provide a PLL circuit in which a free-running oscillation frequency can be adjusted to be constant even when the power supply voltage of the VCO circuit fluctuates, so that stable locking can be realized. Further, it is an object of the present invention to provide a semiconductor device provided with the PLL circuit.
A voltage controlled oscillator circuit (VCO circuit) of the invention includes a control portion to which a first voltage is inputted and from which a second voltage corresponding to the first voltage is outputted, a current source portion to which the second voltage is inputted and from which a current corresponding to the second voltage is outputted, and an oscillator circuit to which the current is inputted and from which a signal with a frequency in accordance with the current is outputted, in which the control portion includes an adjusting circuit, and the adjusting circuit changes the second voltage in conjunction with fluctuation of a power supply voltage.
The adjusting circuit decreases the second voltage when the power supply voltage increases whereas increases the second voltage when the power supply voltage decreases.
A more specific structure of the control portion is as follows.
(First Structure of the Control Portion)
The control portion includes a first transistor, a second transistor, and a third transistor connected in series with the first transistor. The adjusting circuit includes the second transistor. As for the third transistor, a gate and a drain are connected (: hereinafter, called diode-connection). A current flowing through a source and the drain (hereinafter called a drain current) of the third transistor is the sum of a drain current of the first transistor and a drain current of the second transistor. The first voltage is inputted to a gate of the first transistor. The second voltage is outputted from a drain of the first transistor. A third voltage is inputted to a gate of the second transistor. The third voltage changes in conjunction with fluctuation of the power supply voltage.
The second transistor forms a constant current source of supplying a constant current in accordance with the third voltage.
In particular, both of the first transistor and the second transistor are n-channel transistors, and the third voltage decreases when the power supply voltage is increased whereas the third voltage increases when the power supply voltage is decreased. That is, the third voltage changes so as to decrease the drain current of the second transistor when the power supply voltage is increased, whereas the third voltage changes so as to increase the drain current of the second transistor when the power supply voltage is decreased.
In addition, by changing a rate of the drain current of the second transistor with respect to the drain current of the first transistor, a current gain is adjusted. The current gain refers to the amount of change of a current I which flows through the VCO circuit with respect to change of the input voltage Vin of the VCO circuit.
In the first structure of the control portion, a fourth transistor which forms a current mirror circuit together with the third transistor, and a fifth transistor which is connected in series with the fourth transistor and is diode-connected may be further included. Note that conductivity types of the transistors which form the current mirror circuit are the same, gate voltages of the transistors are equal, and so are drain voltages thereof.
(The Second Structure of the Control Portion)
The control portion includes a first transistor, a second transistor, a third transistor connected in series with the first transistor, a fourth transistor, and a fifth transistor connected in series with the fourth transistor. The adjusting circuit includes the second transistor. The third transistor is diode-connected. The fifth transistor is diode-connected. The first transistor and the fifth transistor form a current mirror circuit. A drain current of the third transistor is the sum of a drain current of the first transistor and a drain current of the second transistor. The first voltage is inputted to a gate of the fourth transistor. The second voltage is outputted from a drain of the first transistor. A third voltage is inputted to a gate of the second transistor. The third voltage changes in conjunction with fluctuation of the power supply voltage.
The second transistor forms a constant current source of supplying a constant current in accordance with the third voltage.
In particular, both of the first transistor and the second transistor are p-channel transistors, and the third voltage increases when the power supply voltage is increased whereas the third voltage decreases when the power supply voltage is decreased. That is, the third voltage changes so as to decrease the drain current of the second transistor when the power supply voltage is increased, whereas the third voltage changes so as to increase the drain current of the second transistor when the power supply voltage is decreased.
In addition, by changing a rate of the drain current of the second transistor with respect to the drain current of the first transistor, a current gain is adjusted.
In the second structure of the control portion, a sixth transistor which forms a current mirror circuit together with the third transistor, and a seventh transistor which is connected in series with the sixth transistor and is diode-connected may be further included.
The above is the more specific structures of the control portion.
Note that the present invention can provide a phase-locked loop circuit (PLL circuit) using the above-described voltage controlled oscillator circuit. For example, the invention can have a structure including the above-described voltage controlled oscillator circuit, a frequency divider, a phase comparator, and a loop filter.
A reference signal and an output of the frequency divider are inputted to the phase comparator, and the phase comparator outputs a phase difference between the reference signal and an output signal of the frequency divider. An output of the phase comparator is inputted to the loop filter, and the loop filter removes noise (mainly, a high-frequency component) of the inputted signal to output. An output signal of the loop filter is inputted to the voltage controlled oscillator circuit. An output of the voltage controlled oscillator circuit is inputted to the frequency divider, and the frequency divider decreases the frequency of the inputted signal to 1/N times (N is an arbitrary natural number) to output.
Further, the present invention can provide a semiconductor device provided with the phase-locked loop circuit (PLL circuit). For example, as a semiconductor device, the invention can be applied to a semiconductor device of performing wireless transmission/reception of data. As such a semiconductor device, there are a wireless chip (also called a wireless tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, an RFID tag, an electronic tag, or a transponder), a mobile phone, a cordless phone, a wireless LAN, and the like.
The VCO circuit of the invention can suppress fluctuation of the frequency Fo of an output signal even when a power supply voltage fluctuates since the adjusting circuit is included. In addition, the PLL circuit of the invention can adjust the free-running oscillation frequency to be constant even when the power supply voltage of the VCO circuit fluctuates, so that stable locking can be realized.